Program for Arithmetic Logic Unit (ALU)

Introduction

Hello friends, In this post, we will learn how to write a simple program in VHDL for Arithmetic Logic Unit (ALU).
VHDL has been at the heart of electronic design productivity since initial ratification by the IEEE in 1987. For almost 15 years the electronic design automation industry has expanded the use of VHDL from initial concept of design documentation, to design implementation and functional verification. It can be said that VHDL fueled modern synthesis technology and enabled the development of ASIC semiconductor companies.The editions of Doug Perry’s books have served as the authoritative source of practical information on the use of VHDL for users of the language around the world.

The fact that VHDL is adaptable is a tribute to its architecture. The industry has seen the use of VHDL’s package structure to allow designers, electronic design automation companies and the semiconductor industry to experiment with new language concepts to ensure good design tool and data interoperability. When the associated data types found in the IEEE 1164 standard were ratified, it meant that design data interoperability was possible.

This new generation of electronic designers, along with the current designers of complex systems and ASICs, will find this book as invaluable as the first generation of VHDL users did with the first addition. Updated with current use of the standard, all will benefit from the years of use that have made the VHDL language the underpinning of successful electronic design.

VHDL usage has risen rapidly since its inception and is used by literally tens of thousands of engineers around the globe to create sophisticated electronic products. This chapter will start the process of easing the reader into the complexities of VHDL. VHDL is a powerful language
with numerous language constructs that are capable of describing very complex behavior. Learning all the features of VHDL is not a simple task.

Program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           S : in  STD_LOGIC_VECTOR (2 downto 0);
           O : out  STD_LOGIC_VECTOR (3 downto 0));
end ALU;

architecture Behavioral of ALU is

begin
process(A,B,S)
begin
case S is
when "000"=>
O<=A+B;
when "001"=>
O<=A-B;
when "010"=>
O<=A and B;
when "011"=>
O<=A or B;
when "100"=>
O<=A xor B;
when "101"=>
O<=not A;
when "110"=>
O<=not B;
when others=>
O<=B-A;
end case;
end process;
end Behavioral;